EE380 Assignment 1 Solution

  1. 100% Here's something you know from EE280: how would you implement a decoder with two outputs, o0 and o1, and one select line, s. Write two logic equations for your answer, one for o0 and one for o1.
  2. 100% Which of the following four statements is false?
    Tri-state logic is the prefered method used to ensure that only one of multiple outputs connected to the same bus wire is active at any point in time.
    A multiplexor can be implemented using a decoder and tri-state drivers.
    Per bit, SRAM consumes more power than DRAM.
    Registers often are built using D flip-flops.
    None of the above is false.
  3. 100% Given this processor hardware design, add control states to the following to implement a subtract instruction (as decoded by the when below), such that sub rd,rs,rt yields rd=(rs - rt). You should add initial values and test your design using the simulator before submitting it here. (Hint: pay close attention to the operand order.)
  4. 100% Given this processor hardware design, add control states to the following to implement an add-to-memory instruction (as decoded by the when below), such that addw rs,immed(rt) yields memory[rt + immed] = (rs + memory[rt + immed]). Note that the code given below already implements MIPS "load word" and "store word" instructions... your control logic should work like load, add the value from register rs, and store the result. You should add initial values and test your design using the simulator before submitting it here.
  5. 100% What high-level languages call goto is usually called a jump instruction in assembly language. Given this processor hardware design, add control states to the following to implement an unconditional "jump register" instruction, jr rs, such that PC=rs. This makes the next instruction be fetched from the address given in register rs. You should add initial values and test your design using the simulator before submitting it here.
  6. 100% Given this processor hardware design, suppose that the following control state is the limiting factor in determining the maximum clock speed. Given that the propagation delay associated with SELrs is 10ns, REGout is 5ns, MDRin is 4ns, ALUadd is 20ns, and Zin is 2ns, what is the period (in nanoseconds) of the fastest allowable clock? You may use the simulator to get or check your answer. In any case, give and briefly explain your answer here: 
    SELrs, REGout, MDRin, ALUadd, Zin

EE380 Computer Organization and Design.