LARs (and CRegs)

Line Associative Registers (LARs) are the basis for a new class of processor architectures in which memory accesses are minimized by explicitly managing wide lines of instructions and data in processor registers. They can be viewed as a sort of synthesis between our earlier work on SIMD Within A Register (SWAR) and on Cache-Registers (CRegs). The following publications explain some of the key concepts....

Publications On LARs

The following are publications directly about LARs:

• Matthew Sparks' M.S. Thesis, A Comprehensive HDL Model of a Line Associative Register Based Architecture (PDF), describes a six-stage pipeline using ILARs and DLARs with a decoupled memory system, type-conversion hardware, and type-sensitive execution units.

  @mastersthesis{LAR2013,
   author = {Sparks, Matthew A.},
   title = {A Comprehensive HDL Model of a Line Associative Register Based Architecture},
   school = {University of Kentucky},
   year = {2013},
   note = {http://aggregate.org/LAR/mSparksThesis.pdf}
  }
  

• The most recently published summary of the compiler target model for LARs (available as a PDF preprint):

  @inproceedings{LARSCPC10,
   author={Paul S. Eberhart and Henry G. Dietz},
   title={A Compiler Target Model for Line Associative Registers},
   booktitle = {Compilers for Parallel computing (CPC 2010)},
   month={July},
   year={2010}
  }
  

• Kalyan Ponnala's M.S. Thesis, Instruction Set Architecture Implementation and Design for DATA LARs (PDF, non-final version defended), describes DLARs and a complete Verilog implementation of the processing element pipeline.

  @book{DLAR2010,
   author = {Kalyan Ponnala},
   title = {{Instruction Set Architecture Implementation and Design for DATA LARs}},
   publisher = {M.S. Thesis, University of Kentucky},
   year = {2010}
   }
  

• Nein Lim's M.S. Thesis, Separating Instruction Fetches from Memory Accesses: ILAR (Instruction Line Associative Registers) (PDF), describes the ILAR details, giving a Verilog design and details of instruction block compression.

  @book{ILAR2009,
   author = {Nien Yi Lim},
   title = {{Separating Instruction Fetches from Memory Accesses: ILAR
  (Instruction Line Associative Registers)}},
   publisher = {M.S. Thesis, University of Kentucky},
   url={{http://hdl.handle.net/10225/1121}},
   month={12},
   year = {2009}
   }
  

• Krishna Melarkode's M.S. Thesis, Line Associative Registers (PDF), is the most complete document describing the new concepts in LARs beyond CRegs.

  @book{LAR2004,
   author = {Krishna Melarkode},
   title = {Line Associative Registers},
   publisher = {M.S. Thesis, University of Kentucky},
   url={{http://hdl.handle.net/10225/255}},
   month={October},
   day={11},
   year = {2004}
   }
  

Publications On CRegs

Professor Dietz's 1987 Ph.D. work centered on compiler and language mechanisms for dealing with aliases... so it was not much of a stretch to start thinking in terms of architectural mechanisms to help with the same type of problems. The concept of CRegs also dates from 1987.... The following are publications directly about CRegs.

• Compiler and Architecture Issues with CRegs, slides from Peter Dahl at UMN, December 1, 1994
• Reducing Memory Traffic with CRegs, Peter Dahl and Matt O'Keefe, MICRO 27, November 1994
• The original CRegs paper was published in 1988. CRegs: a new kind of memory for referencing arrays and pointers (PDF) is still the best introduction to the basic concepts.

  @inproceedings{63018,
   author = {H. Dietz and C. H. Chi},
   title = {CRegs: a new kind of memory for referencing arrays and pointers},
   booktitle = {Supercomputing '88: Proceedings of the 1988 ACM/IEEE conference on Supercomputing},
   year = {1988},
   isbn = {0-8186-0882-X},
   pages = {360--367},
   location = {Orlando, Florida, United States},
   publisher = {IEEE Computer Society Press},
   address = {Los Alamitos, CA, USA},
   }
  

Related Publications

The following are publications on related topics:

• Randy Fisher's PhD Thesis
• AITR-1459.pdf
• How to Fake 1000 Registers
• Tolerating Data Access Latency with Register Preloading, Chen, Mahlke, and Hwu, ICS 92
• Speculative Register Promotion Using Advanced Load Address Table (ALAT), Lin, Chen, Hsu, and Yew, 2003
• The Dream Of A Lifetime: A Lazy Variable Extent Mechanism, Steele and Sussman
• p183-gallagher.pdf
• p235-postiff.pdf
• p289-onder.pdf
• p344-chi.pdf
• p51-koes.pdf
• p51-sanchez.pdf
• p58-hammond.pdf
• p67-lin.pdf
• p71-huang.pdf
• p730-heggy.pdf
• post1.pdf
• refs.bib

The only thing set in stone is our name.